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preliminary MX98224EC 24-port dual-speed ethernet switch controller p/n :pm0782 rev. 0.2, apr, 18, 2001 1 features l single chip 24-port 10/100m wire speed ethernet switching controller with all memory embedded l integration of 24-port dual speed, full/half duplex capable media access controllers ( macs) with rmii interfaces l support ieee 802.3x compliant flow control for fdx and back-pressure flow control for hdx l auto-negotiation through mdc/mdio l support source/destination mac address lookup and aging within built-in storage of 8k mac address (4k entries each entry table) l self address learning, forwarding, and filtering schemes l store-and-forward switching operation l 12-group port base vlan with port overlapping l ieee 802.1q cos and two priority queues support based on port, tagging, and tos configurations l address table and phy register access allowed through cpu processor l dynamic buffer management l no head-of-line blocking system support l power on self diagnostic l serial eeprom (93c46) interface for auto- configuration l broadcast storm prevention l serial cpu interface support for system configuration required l three alter/self-diagnostic led interface l cmos, 1.8/3.3v i/o tolerance l 208 pqfp package general description MX98224EC is a stand-alone 10/100m ethernet switch controller with sram embedded which saves 2-3 extra 64kx64 sram cost. any standalone desktop or enterprising ethernet switches can be achieved by simply combining MX98224EC and quad/octal physical devices. all 24 ports are full duplex capable to provide dedicated 20/200m bandwidth connections each port. MX98224EC basically supports store-and-forward switching scheme with two address entry tables, 4k size each. the function modules integrated in controller include 24-port half/full-duplex compatible media access controller with rmii interface, address resolution logic (arl) for address learning, filtering, recognition, priority queue manager, port base vlan. it fully complies with ieee std. 802.3/802.3u/802.1q specifications and supports mdc/mdio interface for physical layer management with industrial standard physical devices. the switch architecture adopting dynamic buffer management shared by 24 ports can reach full-line speed of high performance application. to save system cost, single 50mhz clock is for rmii and system requirement. MX98224EC proceeds in advanced foundry and smaller package which consumes lower power dissipation. the smart features with low power cpu or eeprom are for system configuration and alr access required. also, it emphasizes at class of service ( cos) which extracts various packet types in appropriate forwarding scheme. now, voice over ip ( voip) is applied the feature for cutting voice packet latency and promise the quality of service. in addition, port-base vlan is another valuable feature for the switches. MX98224EC offers 12 groups with port overlapping allowed. the feature can add on more security and data flow in the same switch with different groups should get connection through router. the powerful switching architecture and robust design can easily reach high performance, non-blocking data flow. head-of-line blocking prevents switch performance, and operation defective from other port impacts. the switch architecture provides a clean port independent operation. it guarantees port transmission or receive is not affected by other ports. moreover, user can discard broadcast packets regarding the threshold of system overload. this prevents potential broadcast storming from abnormal events. after buffer fullness drops in the safe margin, the switch controller jumps into flow control state to allow physical ports work as normal condition. MX98224EC provides self on test as soon as power on or reset. it will detect all buffer memory and address table and others. if defective, led is automatically on. several leds are defined in switch controller like status of broadcast storm, packet loss, and buffer full.
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 2 txd_ p[1:0] rxd_ p[1:0] 10/100m ethernet mac eeprom i/f cpu i/f empty table unicast link list mdc/mdio i/f buffer memory 4k address table led i/f pin setting address resolution logic multicast link list registers figure 1. mx9822 4ec functional block diagram mdc mdio crsdv_p clk txen_p prity0 prity23 iodata ecs esk inclk edi leda ledc edo ledb enprity reset cpusel
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 3 figure 2. MX98224EC system block diagram optional components m m x x i i c c 2 2 4 4 - - p p o o r r t t s s w w i i t t c c h h octal phy octal phy transformer octal phy transformer transformer eeprom cpu rs-232
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 4 edo/inclk edi/iodata esk/outclk ecs/cpusel enrom/leda encpu/ledb ledc gnd vdd enprity prity0 prity1 prity2 prity3 prity4 prity5 prity6 prity7 gnd vcc prity8 prity9 prity10 prity11 prity12 prity13 prity14 prity15 prity16 prity17 gnd vdd prity18 prity19 prity20 prity21 prity22 prity23 gnd vcc rxd_23[1] rxd_23[0] crsdv_23 txen_23 txd_23[0] txd_23[1] rxd_22[1] rxd_22[0] crsdv_22 txen_22 txd_22[0] txd_22[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 54 55 56 57 58 59 60 61 63 64 65 67 68 69 70 71 72 74 75 76 77 78 79 80 83 84 85 86 87 88 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208 207 205 203 202 200 199 198 196 195 192 191 190 189 188 187 184 183 182 181 180 179 178 174 172 171 167 166 163 162 161 160 159 MX98224EC txd_0[1] txd_0[0] txen_0 crsdv_0 rxd_0[0] rxd_0[1] txd_1[1] txd_1[0] txen_1 crsdv_1 rxd_1[0] rxd_1[1] txd_2[1] txd_2[0] txen_2 vdd gnd crsdv_2 rxd_2[0] rxd_2[1] txd_3[1] txd_3[0] txen_3 crsdv_3 rxd_3[0] rxd_3[1] txd_4[1] txd_4[0] txen_4 crsdv_4 rxd_4[0] rxd_4[1] vcc gnd txd_5[1] txd_5[0] txen_5 crsdv_5 rxd_5[0] rxd_5[1] txd_6[1] txd_6[0] txen_6 crsdv_6 rxd_6[0] rxd_6[1] vdd gnd txd_7[1] txd_7[0] txen_7 crsdv_7 rxd_21[1] rxd_21[0] crsdv_21 txen_21 txd_21[0] txd_21[1] reset# rxd_20[1] mdio mdc gnd vdd rxd_20[0] crsdv_20 txen_20 txd_20[0] txd_20[1] rxd_19[1] rxd_19[0] crsdv_19 txen_19 gnd vcc txd_19[0] txd_19[1] rxd_18[1] rxd_18[0] crsdv_18 txen_18 txd_18[0] txd_18[1] rxd_17[1] rxd_17[0] crsdv_17 txen_17 gnd vdd txd_17[0] txd_17[1] rxd_16[1] rxd_16[0] crsdv_16 txen_16 txd_16[0] txd_16[1] rxd_15[1] rxd_15[0] crsdv_15 txen_15 txd_15[0] txd_15[1] rxd_14[1] rxd_7[0] rxd_7[1] txd_8[1] txd_8[0] txen_8 crsdv_8 rxd_8[0] rxd_8[1] txd_9[1] vdd gnd txd_9[0] txen_9 crsdv_9 rxd_9[0] rxd_9[1] txd_10[1] txd_10[0] txen_10 crsdv_10 rxd_10[0] vcc gnd rxd_10[1] txd_11[1] txd_11[0] txen_11 clk crsdv_11 rxd_11[0] rxd_11[1] txd_12[1] vdd gnd txd_12[0] txen_12 crsdv_12 rxd_12[0] rxd_12[1] txd_13[1] txd_13[0] txen_13 crsdv_13 vcc gnd rxd_13[0] rxd_13[1] txd_14[1] txd_14[0] txen_14 crsdv_14 rxd_14[0] figure 3. MX98224EC pin diagram top view
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 5 pin description 10/100mbps rmii interface pin# pin name i/o description 4 10 18 24 30 38 44 52 58 66 72 81 89 95 103 109 115 123 129 137 143 154 160 166 crsdv_0 crsdv_1 crsdv_2 crsdv_3 crsdv_4 crsdv_5 crsdv_6 crsdv_7 crsdv_8 crsdv_9 crsdv_10 crsdv_11 crsdv_12 crsdv_13 crsdv_14 crsdv_15 crsdv_16 crsdv_17 crsdv_18 crsdv_19 crsdv_20 crsdv_21 crsdv_22 crsdv_23 i carrier sense/receive data valid active high, indicate receive medium is non-idle. crsdv is asserted asynchronously with respect to clk. 6, 5 12, 11 20, 19 26, 25 32, 31 40, 39 46, 45 54, 53 60, 59 68, 67 76, 73 83, 82 91, 90 99, 98 105, 104 111, 110 117, 116 125, 124 131, 130 139, 138 149, 144 156, 155 162, 161 168, 167 rxd_0[1:0] rxd_1[1:0] rxd_2[1:0] rxd_3[1:0] rxd_4[1:0] rxd_5[1:0] rxd_6[1:0] rxd_7[1:0] rxd_8[1:0] rxd_9[1:0] rxd_10[1:0] rxd_11[1:0] rxd_12[1:0] rxd_13[1:0] rxd_14[1:0] rxd_15[1:0] rxd_16[1:0] rxd_17[1:0] rxd_18[1:0] rxd_19[1:0] rxd_20[1:0] rxd_21[1:0] rxd_22[1:0] rxd_23[1:0] i receive data from port 0 to port 23, synchronous to clk and rxd[1] is msb. while crsdv is deasserted, rxd[1:0] is ? 00 ? .
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 6 3 9 15 23 29 37 43 51 57 65 71 79 88 94 102 108 114 122 128 136 142 153 159 165 txen_0 txen_1 txen_2 txen_3 txen_4 txen_5 txen_6 txen_7 txen_8 txen_9 txen_10 txen_11 txen_12 txen_13 txen_14 txen_15 txen_16 txen_17 txen_18 txen_19 txen_20 txen_21 txen_22 txen_23 o 4ma transmit enable active high, assertion indicates the mac is presenting di-bits on txd[1:0] for transmission. txen is asserted synchronously with first nibble of preamable and remained asserted while all di-bits transmitted are presented on rmii. txen is negated prior to 1 st clk rising edge following the final di-bit of frame. 1, 2 7, 8 13, 14 21, 22 27, 28 35, 36 41, 42 49, 50 55, 56 61, 64 69, 70 77, 78 84, 87 92, 93 100, 101 106, 107 112, 113 118, 119 126, 127 132, 133 140, 141 151, 152 157, 158 163, 164 txd_0[1:0] txd_1[1:0] txd_2[1:0] txd_3[1:0] txd_4[1:0] txd_5[1:0] txd_6[1:0] txd_7[1:0] txd_8[1:0] txd_9[1:0] txd_10[1:0] txd_11[1:0] txd_12[1:0] txd_13[1:0] txd_14[1:0] txd_15[1:0] txd_16[1:0] txd_17[1:0] txd_18[1:0] txd_19[1:0] txd_20[1:0] txd_21[1:0] txd_22[1:0] txd_23[1:0] o 4ma transmit data from port 0 to port 23, synchronous to clk and txd[1] is msb. when txen is asserted, txd[1:0] are accepted fro transmission. txd[1:0] is ? 00 ? when txen is deasserted. 80 clk i reference clock for rmii and system clock use. 50mhz. subtotal 145
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 7 eeprom interface pin# pin name i/o description 204 enrom i eeprom enable internally pull down. default disable. active high; indicated configuration data is auto-loaded from eeprom after reset. tying this pin to ground disables eeprom interface and prevents auto- configuration. 205 ecs o 4ma eeprom chip select active high. 206 esk o 8ma eeprom clock 390khz derived from system clock. 207 edi o 4ma eeprom data input output data to the corresponding edi pin of eeprom. 208 edo i eeprom data output input data to the corresponding edo pin of eeprom. subtotal 5 cos priority setting pin# pin name i/o description 199 enprity i priority queue enable internally pull down. per port base pin setting priority function enable. if the pin is enabled, per port base priority settings used by eeprom or cpu is invalid. port base priority settings controlled by eeprom or cpu will be valid when the pin is pull down. 198-191 188-179 176-171 prity0 prity1 prity2 prity3 prity4 prity5 prity6 prity7 prity8 prity9 prity10 prity11 prity12 prity13 prity14 prity15 prity16 prity17 prity18 prity19 prity20 prity21 prity22 prity23 i per port priority enable active low. if pin pull high, the mapped port will act as high priority.
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 8 subtotal 25 cpu interface pin# pin name i/o description 203 encpu i cpu interface enable internally pull down. at reset, the pin is latched as cpu interface enable. 205 cpusel i cpu selection the selected chip enable from cpu. 206 outclk o 8ma cpu input clock the switch generates 8.3mhz serial clock to cpu. 207 iodata i/o 4ma cpu data input/output cpu read/write data & command. 208 inclk i cpu output clock cpu generates 8.3mhz serial clock to ethernet switch. subtotal 5 led interface pin# pin name i/o description 204 leda o 8ma address table self-test/buffer full led internally pull down. initially, after power on or reset, address table will be tested and ledc (reset function) is keeping on until internal test finished. if any error found in address table, leda will keep on. after ledc off, the switch is functional. if global buffer utilization is full within previous 40ms intervals, leda will be on 40ms. it will keep on if the buffer utilization keeps full within current intervals. 203 ledb o 8ma buffer memory test/packet loss led internally pull down. if power on or reset, ledc (reset function) is keeping on and all buffer memory will be tested. if buffer memory has an error found, ledb will be on. after ledb and ledc off, switch self-test is done. if packet loss found, ledb is keeping on 40ms within each 40ms time intervals. 202 ledc o 8ma reset/broadcast storm led internally pull up. if reset, ledc is on until all internal memory test finished. then, the pin will show the status of broadcast storm packets. if the number of broadcast packets stored in switch over threshold within 40ms time intervals, ledc will be on 40ms. it will be shown until broadcast storm released. subtotal 3
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 9 miscellaneous pin# pin name i/o description 147 mdc i/o 16ma management data clock internal pull down. the pin provides 2.5mhz clock for mdio. 148 mdio i/o 16ma management data bi-directional rmii management port data pin. mdio is synchronous with respect to mdc and is sampled on the rising edge of mdc. 150 reset# i chip reset active low; be held low for some time after power-on. 33, 74, 96, 134, 169, 189, vcc 1.8v core power 16, 47, 62, 85, 120, 145, 177, 200 vdd 3.3v i/o power 17, 34, 48, 63, 75, 86, 97, 121, 135, 146, 170, 178, 190, 201 gnd ground subtotal 31
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 10 eeprom and cpu control registers offset register offset register 0x00h port base vlan group 0 (0-11) 0x1bh aging timer 0x01h port base vlan group 0 (12-23) 0x1ch reserved 0x02h port base vlan group 1 (0-11) 0x1dh 802.3x pause frame timer 0x03h port base vlan group 1 (12-23) 0x1eh mac address 0 0x04h port base vlan group 2 (0-11) 0x1fh mac address 1 0x05h port base vlan group 2 (12-23) 0x20h mac address 2 0x06h port base vlan group 3 (0-11) 0x21h ip/vlan tagging base priority (0-7) 0x07h port base vlan group 3 (12-23) 0x22h ip/vlan tagging base priority (8-15) 0x08h port base vlan group 4 (0-11) 0x23h ip/vlan tagging base priority (16-23) 0x09h port base vlan group 4 (12-23) 0x24h reserved 0x0ah port base vlan group 5 (0-11) 0x25h reserved 0x0bh port base vlan group 5 (12-23) 0x26h reserved 0x0ch port base vlan group 6 (0-11) 0x27h led control & vlan group reset 0x0dh port base vlan group 6 (12-23) 0x28h cpu access data 0x0eh port base vlan group 7 (0-11) 0x29h phy/address table operation command 0x0fh port base vlan group 7 (12-23) 0x2ah flow control enable (8-23) 0x10h port base vlan group 8 (0-11) 0x2bh reserved 0x11h port base vlan group 8 (12-23) 0x2ch flow control enable (0-7) 0x12h port base vlan group 9 (0-11) 0x2dh reserved 0x13h port base vlan group 9 (12-23) 0x2eh reserved 0x14h port base vlan group 10 (0-11) 0x2fh reserved 0x15h port base vlan group 10 (12-23) 0x30h auto-negotiation disable (0-15) 0x16h port base vlan group 11 (0-11) 0x17h port base vlan group 11 (12-23) 0x31h auto-negotiation (16-23) & force speed setting (0-7) 0x18h configuration 0 & port base priority (0-7) 0x32h force speed setting (8-23) 0x19h port base priority (8-23) 0x33h force half/full duplex setting (0-15) 0x1ah configuration 1 0x34h force half/full duplex setting (16-23) note : 1. 93c46 eeprom must be in 16-bit mode 2. the contents of eeprom and cpu access registers are the same as following descriptions 3. (a-b) means port number setting from a to b
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 11 port base vlan group 0 (0-11) (reg00h), default = 0x0fffh bit description type default 0.11-0 port 0-11 vlan group 0 default 1; all ports are into single group. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 0 member r/w 0xfff 0.15-12 n/a port base vlan group 0 (12-23) (reg01h), default = 0x0fffh bit description type default 1.11-0 port 12-23 vlan group 0 default 1; all ports are into single group. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 0 member r/w 0xfff 1.15-12 n/a port base vlan group 1 (0-11) (reg02h), default = 0x0000h bit description type default 2.11-0 port 0-11 vlan group 1 default 0; group 1 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 1 member r/w 0x000 2.15-12 n/a port base vlan group 1 (12-23) (reg03h), default = 0x0000h bit description type default 3.11-0 port 12-23 vlan group 1 default 0; group 1 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 1 member r/w 0x000 3.15-12 n/a
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 12 port base vlan group 2 (0-11) (reg04h), default = 0x0000h bit description type default 4.11-0 port 0-11 vlan group 2 default 0; group 2 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 2 member r/w 0x000 4.15-12 n/a port base vlan group 2 (12-23) (reg05h), default = 0x0000h bit description type default 5.11-0 port 12-23 vlan group 2 default 0; group 2 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 2 member r/w 0x000 5.15-12 n/a port base vlan group 3 (0-11) (reg06h), default = 0x0000h bit description type default 6.11-0 port 0-11 vlan group 3 default 0; group 3 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 3 member r/w 0x000 6.15-12 n/a port base vlan group 3 (12-23) (reg07h), default = 0x0000h bit description type default 7.11-0 port 12-23 vlan group 3 default 0; group 3 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 3 member r/w 0x000 7.15-12 n/a
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 13 port base vlan group 4 (0-11) (reg08h), default = 0x0000h bit description type default 8.11-0 port 0-11 vlan group 4 default 0; group 4 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 4 member r/w 0x000 8.15-12 n/a port base vlan group 4 (12-23) (reg09h), default = 0x0000h bit description type default 9.11-0 port 12-23 vlan group 4 default 0; group 4 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disa ble; to be treat as an isolated port 1 : enable; to be a group 4 member r/w 0x000 9.15-12 n/a port base vlan group 5 (0-11) (reg0ah), default = 0x0000h bit description type default a.11-0 port 0-11 vlan group 5 default 0; group 5 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 5 member r/w 0x000 a.15-12 n/a port base vlan group 5 (12-23) (reg0bh), default = 0x0000h bit description type default b.11-0 port 12-23 vlan group 5 default 0; group 5 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 5 member r/w 0x000 b.15-12 n/a
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 14 port base vlan group 6 (0-11) (reg0ch), default = 0x0000h bit description type default c.11-0 port 0-11 vlan group 6 default 0; group 6 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolat ed port 1 : enable; to be a group 6 member r/w 0x000 c.15-12 n/a port base vlan group 6 (12-23) (reg0dh), default = 0x0000h bit description type default d.11-0 port 12-23 vlan group 6 default 0; group 6 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 6 member r/w 0x000 d.15-12 n/a port base vlan group 7 (0-11) (reg0eh), default = 0x0000h bit description type default e.11-0 port 0-11 vlan group 7 default 0; group 7 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 7 member r/w 0x000 e.15-12 n/a port base vlan group 7 (12-23) (reg0fh), default = 0x0000h bit description type default f.11-0 port 12-23 vlan group 7 default 0; group 7 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 7 member r/w 0x000 f.15-12 n/a
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 15 port base vlan group 8 (0-11) (reg10h), default = 0x0000h bit description type default 10.11-0 port 0-11 vlan group 8 default 0; group 8 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 8 member r/w 0x000 10.15-12 n/a port base vlan group 8 (12-23) (reg11h), default = 0x0000h bit description type default 11.11-0 port 12-23 vlan group 8 default 0; group 8 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 8 member r/w 0x000 11.15-12 n/a port base vlan group 9 (0-11) (reg12h), default = 0x0000h bit description type default 12.11-0 port 0-11 vlan group 9 default 0; group 9 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 9 member r/w 0x000 12.15-12 n/a port base vlan group 9 (12-23) (reg13h), default = 0x0000h bit description type default 13.11-0 port 12-23 vlan group 9 default 0; group 9 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disa ble; to be treat as an isolated port 1 : enable; to be a group 9 member r/w 0x000 13.15-12 n/a
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 16 port base vlan group 10 (0-11) (reg14h), default = 0x0000h bit description type default 14.11-0 port 0-11 vlan group 10 default 0; group 10 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be treat as an isolated port 1 : enable; to be a group 10 member r/w 0x000 14.15-12 n/a port base vlan group 10 (12-23) (reg15h), default = 0x0000h bit description type default 15.11-0 port 12-23 vlan group 10 default 0; group 10 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 10 member r/w 0x000 15.15-12 n/a port base vlan group 11 (0-11) (reg16h), default = 0x0000h bit description type default 16.11-0 port 0-11 vlan group 11 default 0; group 11 not in use if all zero. one bit per port; e.g. bit 0 for port 0 and bit 11 for port 11 0 : disable; to be t reat as an isolated port 1 : enable; to be a group 11 member r/w 0x000 16.15-12 n/a port base vlan group 11 (12-23) (reg17h), default = 0x0000h bit description type default 17.11-0 port 12-23 vlan group 11 default 0; group 11 not in use if all zero. one bit per port; e.g. bit 0 for port 12 and bit 11 for port 23 0 : disable; to be treat as an isolated port 1 : enable; to be a group 11 member r/w 0x000 17.15-12 n/a
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 17 configuration 0 and port base priority (0-7) (reg18h), default = 0x0022h bit description type default 18.0 continuous 16-time collision drop disable 0 : packet that runs into 16 consecutive collision will be dropped 1 : packet that runs into 16 consecutive collision will not be dropped r/w 0 18.1 timeout disable 0 : packet will not be dropped if packet has been queued over 1 second 1 : packet will be dropped in spite of packet being queue over 1 second r/w 1 18.3-2 crc hashing selection 48-bit da/sa address is translated separated into 12-bit entry pointer of address table for address learning and recognition. the translation is by aid of crc generator within the switch controller. the index of entry pointer selection is defined by: 00 : bit [11:0] of crc are selected 01 : bit [16:5] of crc are selected 10 : bit [24:13] of crc are sel ected 11 : bit [30:19] of crc are selected r/w 00 18.4 direct mapping it means bit [63:52] of da/sa address directly as an index of address table. 0 : crc calculation to get the hashing index of address table 1 : direct mapping enable r/w 1 18.5 reserved r/w 0 18.6 n/a 18.7 reserved r/w 1 18.15-8 port 0-7 priority port base priority settings from port 0 to port 7. if external pins of port base priority are set, the content of eeprom or cpu will be overridden. one bit per port; e.g. bit 8 for port 0 and bit 15 for port 7. 0 : disable 1 : enable, the port of packets always in high priority r/w 0x00h port base priority (8-23) (reg19h), default = 0x0000h bit description type default 19.15-0 port 8-23 priority port base priority settings from port 8 to port 23. if external pins of port base priority are set, the content of eeprom or cpu will be overridden. one bit per port; e.g. bit 0 for port 8 and bit 15 for port 23. 0 : disable 1 : enable, the port of packets always in high priority r/w 0x0000h
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 18 configuration 1 (reg1ah), default = 0x502eh bit description type default 1a.3-0 reserved r/w 0xfh 1a.5-4 backoff operation mode in normal backoff algorithm, packet transmission delays a random time within 2 n ? 1 slot time (1 slot time = 512 bit times) when collision occurs. the switch provides some modification of backoff algorithm to improve ethernet performance on half- duplex connection. 00 : standard operation. 01 : first two collisions follow standard backoff. more than two collisions in transmission, packet resend delays 0-3 slot times. 10 : packet resend delays 0 slot time only when port buffer full. 11 : packet resend delays 0 slot time all the time. r/w 00 1a.6 back pressure disable enable back pressure on half duplex connection for all ports 0 : enable 1 : disable r/w 0 1a.7 n/a 1a.8 reserved r/w 0 1a.14-9 high/low priority ratio bit 9 to 11 means a decimal value for low priority packets to be transmitted whereas bit 12 to 14 to a decimal value for high priority packets. followings are some example of high to low priority value. r/w 0x28h high priority value low priority value bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 0/1 0/1 0/1 0 0 0 0 1 1 0 0 1 meaning high priority port packets need to be sent first until empty; then, low priority packets the transmission ratio of high to low priority packets is 3 : 1 1a.15 aging out enable the function of aging out from address table. 0 : enable 1 : disable r/w 0 aging timer (reg1bh), default = 0x0005h bit description type default 1b.15-0 aging timer provides for address table. the timer period is defined to age out the least unused entries on address table. the formula is age_timer (bit 0-15) x 65536 x 1ms. here are some examples: bit 15 ? bit 0 aging timer 0x0001h 65.5 sec (around 1 min) 0x0005h 3 27.7 sec (around 5.5 min) 0x001bh 1769.5 sec (around 30 min) 0x0037h 3604.5 sec (around 1 hr) r/w 0x0005h
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 19 reserved (reg1ch), default = 0xc350h bit description type default 1c.15-0 reserved r/w 0xc350h 802.3x pause frame timer (reg1dh), default = 0x01ffh bit description type default 1d.4-0 reserved r/w 0x1fh 1d.15-5 flow control counter the timer determines the period, namely ? pause time ? , to inhibit packet transmission from attached host for flow control. the variable pause time of pause frame is equal to the decimal value times 32 plus 31 slot time. r/w 0x1e0h mac address 0 (reg1eh), default = 0x0000h bit description type default 1e.15-0 switch ? s mac id for address bit [15:0] r/w 0x0000h mac address 1 (reg1fh), default = 0x0000h bit description type default 1f.15-0 switch ? s mac id for address bit [31:16] r/w 0x0000h mac address 2 (reg20h), default = 0x0000h bit description type default 20.15-0 switch ? s mac id for address bit [47:32] r/w 0x0000h ip/vlan tagging base priority (0-7) (reg21h), default = 0x0000h bit description type default 21.7-0 tos (ip base) enable for port 0-7 to recognize the tos field of ip priority packets. one bit per port; e.g. bit 0 for port 0 and bit 7 for port 7. 0 : disable 1 : enable r/w 0x00h 21.15-8 tci (vlan tagging base) enable for port 0-7 to recognize the tci field of vlan priority packets. one bit per port; e.g. bit 8 for port 0 and bit 15 for port 7. 0 : disable 1 : enable r/w 0x00h
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 20 ip/vlan tagging base priority (8-15) (reg22h), default = 0x0000h bit description type default 22.7-0 tos (ip base) enable for port 8-15 to recognize the tos field of ip priority packets. one bit per port; e.g. bit 0 for port 8 and bit 7 for port 15. 0 : disable 1 : enable r/w 0x00h 22.15-8 tci (vlan tagging base) enable for port 8-15 to recognize the tci field of vlan priority packets. one bit per port; e.g. bit 8 for port 8 and bit 15 for port 15. 0 : disable 1 : enable r/w 0x00h ip/vlan tagging base priority (16-23) (reg23h), default = 0x0000h bit description type default 23.7-0 tos (ip base) enable for port 16-23 to recognize the tos field of ip priority packets. one bit per port; e.g. bit 0 for port 16 and bit 7 for port 23. 0 : disable 1 : enable r/w 0x00h 23.15-8 tci (vlan tagging base) enable for port 8-15 to recognize the tci field of vlan priority packets. one bit per port; e.g. bit 8 for port 16 and bit 15 for port 23. 0 : disable 1 : enable r/w 0x00h reserved (reg24h), default = 0xb081h bit description type default 24.15-0 reserved r/w 0xb081h reserved (reg25h), default = 0x0040h bit description type default 25.15-0 reserved r/w 0x0040h reserved (reg26h), default = 0x0082h bit description type default 26.15-0 reserved r/w 0x0082h
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 21 led control and vlan group reset (reg27h), default = 0x0200h bit description type default 27.0 port grouping command when, initially, the execution of default values of the vlan registers (reg00h-17h) or vlan grouping settings required via cpu/eeprom, vlan grouping contents need to write into the registers; then, grouping command is put into action. after grouping command is done, the bit will be self-clean to 0. 0 : idle 1 : port regrouping enable r/w 0 27.2-1 reserved r/w 00 27.3 broadcast storm led 0 : led displays the broadcast storm symptom in high priority packets 1 : led displays the broadcast storm symptom of all packets r/w 1 27.4 packet loss led 0 : led displays the high priority packet loss 1 : led displays all packet loss r/w 1 27.15-5 n/a 0x010h cpu access data (reg28h), default = 0x0000h bit description type default 28.15-0 access data generally, bit 15-0 is the access data for phy registers and address table. in case, cpu requires to select phy id and register number before phy register access. the starting phy id for the switch is 0. bit 4-0 can be presented for phy register number and bit 9-5 for phy id in address selection of phy registers operation. r/w 0x0000h phy/address table operation command (reg29h), default = 0x0000h bit description type default 29.0 cpu action if cpu takes read/write actions to address table or phy registers, set the bit on. after action done, the bit will be self-clean to 0. 0 : idle 1 : cpu action r/w 0 29.1 cpu read/write read or write action set to address table or phy registers. 0 : read operation 1 : write operation r/w 0 29.2 phy/alr selection cpu access to phy or address table 0 : phy access 1 : address table access r/w 0
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 22 29.5-3 phy/alr command in phy register access 000 : a searching function for phy id and phy register number when cpu access data filled relevant information. 001 : a command for switch internal control register to cpu access data based on read operation or a command for cpu access data to register to switch internal control register based on write operation. 100 : a command for content of phy registe r to switch internal control register based on read operation or a command for switch internal control register to phy register based on write operation. in address table access 000 : mac id for address bit [15:0] access from cpu access data to switch internal control register based on cpu write operation. it also can be mac id access bit [15:0] from switch internal control register to cpu access data based on cpu read operation. 001 : mac id for address bit [31:16] access from cpu access data to internal control register and based on cpu write operation; and vice versa. 010 : mac id for address bit [47:32] access from cpu access data to switch internal control register based on cpu write operation; and vice versa. 011 : status of address table entry acces s like port number bit [8:4], aging timer bit [3:1], and valid bit [0] from switch internal control register to cpu access data based on cpu read operation. 100 : based on read operation from content of an address table entry to switch internal control register or write operation from switch internal control register to content of an address table entry. r/w 0x0h 29.10-6 frozen port the switch provides frozen function for an entry in address table; that is, an entry with learned mac address and port number as an input will protect not to be aging out when the port number and assigned mac have been set. frozen function can only work on the first layer of address table. it ? s because the entry of second-layer of address table should be for dynamic mac address. if frozen port sets to all one and cpu read/write command is one, the frozen mac address will be released. if frozen port sets all one and cpu read/write command is zero, the host processor will read the content of second layer of address table. r/w 0x00h 29.15-11 reserved r/w 0x00h flow control enable (8-23) (reg2ah), default = 0x0000h bit description type default 2a.15-0 flow control enable ieee 802.3x flow control for port 8-23. one bit per port; e.g. bit 0 for port 8 and bit 15 for port 23. 0 : disable 1 : enable r/w 0x0000h
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 23 reserved (reg2bh), default = 0xffffh bit description type default 2b.15-0 reserved r/w 0xffffh flow control enable (0-7) (reg2ch), default = 0x00ffh bit description type default 2c.7-0 reserved r/w 0xffh 2c15-8 flow control enable ieee 802.3x flow control for port 0-7. one bit per port; e.g. bit 8 for port 0 and bit 15 for port 7. 0 : disable 1 : enable r/w 0x00h reserved (reg2dh), default = 0x0000h bit description type default 2d.15-0 reserved r/w 0x0000h reserved (reg2eh), default = n/a bit description type default 2e.15-0 reserved ro n/a reserved (reg2fh), default = n/a bit description type default 2f.15-0 reserved ro n/a auto-negotiation (0-15) (reg30h), default = 0x0000h bit description type default 30.15-0 auto-negotiation disable auto-negotiation operation of mdio. when port base auto-negotiation disable, the switch port will not listen the final response from phy. one bit per port; e.g. bit 0 for port 0 and bit 15 for port 15. 0 : enable auto-negotiat ion 1 : disable auto-negotiation r/w 0x0000h
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 24 auto-negotiation (16-23) & force speed setting (0-7) (reg31h), default = 0xff00h bit description type default 31.7-0 auto-negotiation disable auto-negotiation operation of mdio. when port base auto-negotiation disable, the switch port will not listen the final response from phy. one bit per port; e.g. bit 0 for port 16 and bit 7 for port 23. 0 : enable auto-negotiation 1 : disable auto-negotiation r/w 0x00h 31.15-8 force speed operation when auto-negotiation off, the port will be set at fixed speed. in eeprom, force settings will be automatically written into phy registers at initialization. force settings by cpu requires extra cpu write operation into phy; so port-base speed operations can keep consistency. one bit per port; e.g. bit 8 for port 0 and bit 15 for port 7. 0 : force 10mbps 1 : force 100mbps r/w 0xffh force speed setting (8-23) (reg32h), default = 0xffffh bit description type default 32.15-0 force speed operation one bit per port; e.g. bit 0 for port 8 and bit 15 for port 23. 0 : force 10mbps 1 : force 100mbps r/w 0xffffh force half duplex setting (0-15) (reg33h), default = 0xffffh bit description type default 33.15-0 force half duplex operation when auto-negotiation off, the port will be set at fixed duplex. in eeprom, force settings will be automatically written into phy registers at initialization. force settings by cpu requires extra cpu write operation into phy; so port-base duplex operations can keep consistency. one bit per port; e.g. bit 0 for port 0 and bit 15 for port 15. 0 : force half duplex 1 : force full duplex r/w 0xffffh force half duplex setting (16-23) (reg34h), default = 0x00ffh bit description type default 34.7-0 force half duplex operation one bit per port; e.g. bit 0 for port 16 and bit 7 for port 23. 0 : force half duplex 1 : force full duplex r/w 0xff 34.15-8 n/a
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 25 functional description clocks MX98224EC requires a unique 50mhz clock signal for both rmii and system requirement at clk input pin. also, the switch generates an 8.3mhz output clock to cpu and the processor feedback the same clock rate back to the switch. the 2.5mhz clock applies on mdc/mdio interface and 390khz refers eeprom interface. reset when power on, a hard reset is initiated by an active low pulse on reset# pin. the initialization process loads all ports configurable parameters, resets internal state machines to idle, initializes embedded memory and address table. at the completion of the reset sequence, all ports are presented for packet transmission and reception. rmii interface reduced media independent interface (rmii) comprises a low pin count intended for use between ethernet phys and switch asics. the management interface (mdc/mdio) is assumed to be identical to that defined in ieee 802.3u. the rmii specification has been optimized for using in high port density interconnect devices which require independent treatment of the data paths. the primary motivator is a switch asic which requires independent data streams between the mac and phy. clk clk is a continuous clock that provides the timing reference for crsdv_0-23, rxd_0-23[1:0], txen_0-23, and txd_0-23[1:0]. the switch choose to provide clk as an input for system and rmii use and each phy device shall have an input corresponding to this clock but may use a single clock input for multiple phys implemented on a single ic. carrier sense/receive data valid crsdv_0-23 shall be asserted by the phy when the receive medium is non-idle. the specifics of the definition of idle for 10base-t and 100base-x are contained in ieee 802.3 and ieee 802.3u. crsdv0-23 is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. that is, in 10base-t mode, when squelch is passed or, in 100base-x mode, when 2 non-contiguous zeroes in 10 bits are detected carrier is said to be detected. if the phy has additional bits to be presented on rxd_0-23[1:0] following the initial deassertion of crsdv_0-23, then the phy shall assert crsdv_0-23 on cycles of clk which present the second di -bit of each nibble and deassert crsdv_0-23 on cycles of clk which present the first di -bit of a nibble. receive data rxd_0-23[1:0] shall transition synchronously to clk. for each clock period in which crsdv_0-23 is asserted, rxd_0-23[1:0] transfers two bits of recovered data from the phy. in some cases, for example before data recovery or during error conditions, a pre-determined value for rxd_0-23[1:0] is transferred instead of recovered data. rxd_0-23[1:0] shall be ? 00 ? to indicate idle when crsdv_0-23 is deasserted. values other than ? 00 ? on rxd_0- 23[1:0] while recovered from crsdv_0-23 is de-asserted shall be ignored by the mac. upon assertion of crsdv_0-23, the phy shall ensure that rxd_0-23[1:0] is equal to ? 00 ? until proper receive decoding takes place. transmit enable txen_0-23 indicates that the mac is presenting di-bits on txd_0-23[1:0] for transmission. txen_0-23 shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are presented. txen_0-23 shall be negated prior to the first clk rising edge following the final di-bit of a frame. txen_0-23 shall transition synchronously with respect to clk. transmit data txd_0-23[1:0] shall transition synchronously with respect to clk. when txen_0-23 is asserted, txd[1:0] are accepted for transmission by the phy. txd_0-23[1:0] shall be ? 00 ? to indicate idle when txen_0-23 is deasserted. values other than ? 00 ? on txd_0-23[1:0] while txen_0-23 is deasserted shall be ignored by the phy.
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 26 phy management the phy determines the operation mode of each port, which are classified as 10mbps-half duplex, 10mbps-full duplex, 100mbps-half duplex, 100mbps-full duplex. the mac of each port is connected to the phy through rmii interface. the phy starting id mapped to the switch is zero. the switch supports phy management through the serial mdc/mdio interface. the switch will continuously read the registers of each phy based on phy id to get the latest information such as link status, speed, operation mode of each port while it is in auto-negotiation. when a port of the switch forced at fixed operation mode, it will not listen any response from the phy through mdc/mdio so that consistent speed and duplex in phy as well as switch is required in force operation mode. frame reception the frame received on 2-bit wide receive channel of rmii interface is queued in receive fifo, and then stored into embedded buffer memory. several error conditions will be identified during data reception. 1.runt frame error, if the frame size is less than 64 bytes; 2.crc error, if fcs is not matched to the result of crc calculation; 3.long frame error, if frame size is larger than 1536 bytes; 4.alignment error, if frame length is of non-integral number of octets; the above frames will be discarded. if no errors have been detected, the frame is stored and forwarded to egress port at wire speed. several pages of buffer memory could be occupied for frame storage, on each page free memory is allocated. the data link management frames, namely ieee 802.3x "pause" frame is recognized and no frame storage occurs. frame transmission frame transmission begins while the output queue of physical port is not empty. the frame data is moved to output fifo from embedded buffer memory, and converted to 2-bit stream through transmit channel of rmii interface. MX98224EC transmits frames in accordance to ieee 802.3 standard. the egress port is responsible for preamble insertion, collision back-off, and inter packet gap keeping. while late collision happens on half-duplex port, the transmitted frame is aborted. if a packet has continuously met 16-time collisions, it will be dropped and the packet will be recovered by upper protocol. in full-duplex mode, the egress port ignores the signaling of carrier activity and collision detection on channel media. broadcast storm control three types of frames are viewed as broadcast frames in MX98224EC: 1. received frame with dl_da as ff-ff-ff-ff-ff-ff 2. received frame with dl_da as 1 ?-??- ??- ??- ??- ?? 3. received frame with unknown destination ( unicast or multicast) address to prevent network melted down, a state of complete network overload, due to broadcast storm (incorrect packet broadcast on a network that cause almost all hosts respond at once and hence storming the network with broadcast packets), users can program to restrict the storage amount of broadcast frames in MX98224EC. while the storage of broadcast frame goes over the threshold, the next coming broadcast frame(s) is dropped. flow control flow control is implemented to avoid abnormal packet drop due to traffic congestion on egress ports. basically, alternative back-pressure mechanism uses jam packet in half-duplex and 802.3x pause frame does in full-duplex mode. flow control is active or inactive based on the internal per port and global reception thresholds in buffer. the switch implements standard 802.3x flow control whose frame is defined as follow.
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 27 the diagram shown above is ieee 802.3x pause frame format whereas da presented for destination mac adress, sa for source mac address, pause frame type defined as 0x8808, opcode for pause operation (0x0001), default pause time for the switch to be 0x1fff, and pad for all zero. the value of pause timer is changable by eeprom or cpu. da field of pause frame should be 0x0180c2000001 before transmission. address learning and recognition after a good packet is received, address resolution logic begins address lookup. the destination mac address and source mac address associated are retrieved. the source mac address is used to build up an address table. by searching the address table, if a unicast destination mac address is recognized, the stored frame is forwarded to destined port. initially, a unicast destination mac address of a packet does not know the outgoing port number so that the stored frame is forwarded as a broadcast packet. in both of address learning and recognition, 48-bit mac address is converted into a 12-bit search index via hash transformation. the switch offers two different hashing schemes; one is called direct mapping and the other is crc mapping. in learning, an entry designated by the search index is checked to be valid or not. if non-valid, a new entry is generated with putting the information of source mac address and ingress port number. a 2-layer structure is provided in learning mechanism. if valid, the 2-layer mechanism can keep 2 different mac addresses in one certain entry to increase hashing resolution. if congestion found for an entry of the 2-layer structure, switch will compare the two numbers of the aging timer and replace the mac record with older aging time to the new mac. in recognition, the mac address in table entry designated by search index is used to compare with destination mac address. if both are matched, the associated port number in address table entry is the destination port. otherwise, the received frame will be classified as a broadcast frame, and be flooded through every port (except source port). t he memory space within MX98224EC can keep up to 8k mac addresses. aging mechanism is supported, namely the address information is aged out if not be referred in 300sec (default, the parameter is programmable). and, the entry of the record can be for newly learnt macs kept in table. 2-priority queue class of service ( cos) class of service denotes the classification of traffic used to differentiate services among traffic classes. MX98224EC offers 2-level priority (high and low) queues, which catch the priority information in the tos field , port base, or vlan tag in the incoming frames as standard ieee 802.1q defines. in this way, the switch controller guarantees the service for high priority frames to some extent, depending on the load condition of incoming traffic. (at least, the high priority service offers better than that of best effort serv i ce . ) it also provides different service ratio settings for users to shape the prioritized frame s on the stream s in the incoming traffic. port-based vlan a virtual lan (vlan) is a broadcast domain or a network segment which enables multiple stations on different physical locations to communicate with each other as if they were on the same lan. with all the advantages such as increasing performance, bandwidth utilization efficiency and security as well as preventing broadcast storm, port- based vlan is the most practical and economical form of vlan. MX98224EC support s up to 12 port-based vlan groups which applies the overlapped vlan scheme. that is, the 24 switch ports can be divided into 12 vlan port-groups. by configuring the port with its vlan membership, each port is assigned to one or more (up to 12) groups. ports belonging to different groups are independent, which means 6 octets 6 octets 2 octets 2 octets 2 octets 42 octets da sa type opcode pause_time pad 802.3x pause frame format
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 28 their network activity or fundamental network broadcasting will not affect or get distributed across those vlan groups to each other. in this way, it can reduce the need for unwanted traffic in the network. moreover, the damaged/abnormal port s can be isolated by removing them from vlan groups' list , so as to prevent network meltdown. port-based vlan in MX98224EC is also very flexible that every port can be shared by multiple groups as the "trunk port" while the other unshared ports are remained independent. queue management MX98224EC utilizes the store-and-forward switching scheme, which needs memory for frame reception and transmission buffering. in MX98224EC, the embedded buffer memory is partitioned into pages which dynamically allocate s the related frame data and switching information. the buffer management control unit dispatches pointers pointing to those pages upon frames reception of the egress ports. for unicast frames, the occupied buffer pages are released after the corresponding ports complete transmission. their pointers are returned to buffer management control unit for reuse. for broadcast frames, the switch controller count the times of transmission of the same broadcast frame till all ports finish the broadcast transmission, then the occupied memory space are released to the free buffer pool. since there are various kinds of page/pointer requests for the buffer management, a queue manager is used in MX98224EC to handle those access requests. via a proprietary arbitration method, the queue manager grants fair enough throughput for each port to transmit at wire speed. 93c46 eeprom interface provide serial interface to load the values of external eeprom which switch can configure in advance. at initial stage, switch will loads the data to internal registers and operates as expected. either eeprom or cpu interface can be used once a time. cpu interface MX98224EC provides another powerful way to configure the value of register via cpu, which can access its as well as phy registers and the address table at any time. basically, mac address look up, content of address table status and frozen a dedicated address are the major function for cpu access through address table. following is the basic system diagram for the connection of host processor, switch, and phy. host processor MX98224EC switch octal phy octal phy octal phy outclk inclk iodata mdc mdio serial management block diagram via switch and phy
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 29 the switch generates an outclk clock to host processor and the same frequency will be back to the switch via inclk pin. there is a data format defined under below table which specifies a communication between the host processor and switch at serial iodata pin. iodata and mdio are bi-direction i/o. the serial management format starts with start bit, then, follows operator, 10-bit register address, turn around, 16-bit content of data, and an idle bit. a command/response from host processor to the switch registers, reg28h and reg29h, can be given based on read/write operation, register address selection, and data. command start bit operator register address turn around data idle read 01 10 aaaaaaaaaa z0 dddddddddddddddd z write 01 01 aaaaaaaaaa 10 dddddddddddddddd z led interface MX98224EC has three leds. at initial stage, these represent address table self-test, memory test, and reset status respectively. and at normal state, these represent buffer full, packet loss, and broadcast storm status. users can monitor the status of switch network via the leds.
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 30 timing diagram reset and clock timing t# description min typ max unit .t01 system clock period 20 20.2 ns .t02 system clock high time 9 10 11 ns .t03 reset# low pulse duration 1 ms t01 t03 t02 clk reset#
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 31 phy management (mdio) reading timing t# description min typ max unit .t11 mdc high time 200 ns .t12 mdc clock period 400 ns .t13 mdc falling edge to mdio delay 3 8 ns .t14 mdc falling edge to mdio hi-z 3 8 ns .t15 mdio setup time 2 ns .t16 mdio hold time 2 ns t16 t15 t11 mdc mdio register address q15 q0 ta t14 t12 t13
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 32 rmii interface timing t# description min typ max unit .t21 clk high time 9 10 11 ns .t22 clk clock period 20 ns .t23 clk to txen delay 3.5 10.5 ns .t24 clk to txd delay 3.5 11.5 ns .t25 crsdv setup time 0 ns .t26 crsdv hold time 4 ns .t27 rxd setup time 0 ns .t28 rxd hold time 4 ns t27 t25 t24 clk csrsdv txen txd rxd t21 t22 t23 t26 t28
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 33 eeprom interface timing t# description min typ max unit .t31 esk clock 2560 ns .t32 93c46 chip enable 27 esk .t33 93c46 command input cycle 10 esk .t34 93c46 data output cycle 17 esk .t35 93c46 data input setup time 3 ns .t36 93c46 data input hold time ns .t37 93c46 chip select setup time 3 ns .t38 93c46 chip select hold time ns .t39 93c46 data output setup time 3 ns .t310 93c46 data output hold time ns t35 esk edo ecs edi sb op op a5 a0 0 d15 d0 t31 t32 t33 t34 t36 t37 t38 t310 t39
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 34 cpu interface timing t# description min typ max unit .t41 cpu clock period 120 ns .t42 data io setup timing 10 ns .t43 chip select setup timing 10 ns .t44 data io hold timing 10 ns .t45 chip select hold timing 10 ns .t46 chip select period 3840 ns clk data io cpusel t41 t46 t43 t45 t42 t44
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 35 electronical specification absolute maximum rating parameter symbol min max unit i/o supply voltage v dd -0.5 4.6 v core supply voltage v cc -0.5 2.5 v input voltage v i -0.5 6 v output voltage v o -0.5 6 v storage temperature t stg -65 150 c operation temperature t opr -40 125 c latch-up current t lat m a recommended operating conditions parameter symbol min max unit i/o supply voltage v dd 3.0 3.6 v core supply voltage v cc 1.62 1.98 v operating temperature t opr 0 70 c power dissipation junction temperature t j 0 125 c low-level input voltage v il -0.3 0.8 v high-level input voltage v ih 2.0 5.5 v dc characteristics parameter symbol min max unit output high voltage v oh 2.4 v output low voltage v ol 0.4 v high impedance state output current i oz 1 a output high current (@v oh = 2.4v ) i oh 6.2 76.0 m a output low current (@v ol = 0.4v) i ol 4.5 30.3 m a input high voltage v ih input low voltage v il supply current i cc m a
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 36 package information
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 37 revision history revision description page date 0.2 speed/duplex settings change to force from reg31h to reg34h 24 04/18/2001
MX98224EC p/n :pm0782 rev. 0.2, apr, 18, 2001 38 top side marking MX98224EC line 1 : MX98224EC is mxic part no. ? e ? : pqfp ? c ? : commercial grade c0013 line 2 : assembly date code. f4004493 7b1 line 3 : wafer lot no. 36cax line 4 : ? 36c ? : revision code ? a ? : bonding option ? x ? : not used taiwan line 5 : state m acronix i nternational c o. , l td. headquarters: tel :+886-3-578-6688 fax :+886-3-563-2888 europ office: tel :+32-2-456-8020 fax :+32-2-456-8021 japan office: tel :+81-44-246-9100 fax :+81-44-246-9105 singapore office: tel :+65-348-8385 fax :+65-348-8096 taipei office: tel :+886-2-2509-3300 fax :+886-2-2509-2200 m acronix a merica, i nc. tel :+1-408-453-8088 fax :+1-408-453-8488 chicago office tel :+1-847-963-1900 fax :+1-847-963-1909 http://www.macronix.com

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